The fabrication of a modem integrated circuit having millions of devices therein is a complex and expensive process. Hence, the design of the integrated circuit and corresponding fabrication details are subjected to numerous tests prior to actually fabricating a device to prevent errors that waste valuable time and money. The fabrication process typically starts with a schematic that represents the circuit from an electrical point of view. That schematic representation is typically input to computer-based simulators that verify that the circuit should work as intended.
For the purpose of fabrication, the various devices and connecting wires in the schematic are laid out on the surface of an integrated circuit substrate. A large scale integrated circuit is represented by geometrical structures (usually polygons) on a series of masks that are used in the fabrication process. The collection of such structures that represents the integrated circuit will be referred to as the geometrical representation of the integrated circuit in the following discussion. The circuit designer typically uses a set of computer aided design (CAD) tools to generate the geometrical representation from the schematic and information about the physical placement of the devices on the integrated circuit substrate. Since there are millions of polygons in the graphical representation, there is a significant probability that the graphical representation has errors. That is, the device and interconnect defined by the graphical representation are electrically different than the device and interconnect defined by the circuit schematic. Accordingly, a design check in which the graphical representation is compared to the schematic representation is utilized.
One such design check is referred to as a layout versus schematic (LVS) check. In this design check, the graphical representation of the circuit is used to generate a netlist for the underlying circuit. A netlist is also generated from the circuit schematic. If the two netlists do not agree, then there is an error in the graphical representation of the circuit. For the purposes of the present discussion, a netlist is a listing of the various “nets” in the integrated circuit. A net consists of all conductive elements that are electrically connected to each other to form a single continuous conductor and the pins of the devices that are connected to that net.
The generation of a netlist from the graphical representation of the circuit requires that the generating program be able to identify the devices and interconnects based on the shapes and relationships of those shapes as the shapes are described in the graphical representation of the circuit. Typically, the netlist generation is divided into two parts. First, a device recognition engine extracts a list of devices, the conducting graphical structures included in those devices that represent the device pins, and conducting graphical structures that represent interconnects from the graphical representation. Next, a netlist comparison engine compares the nets generated from the schematic with the conducting structures and devices from the graphical representation to determine if each net in the schematic is found in the output of the device recognition engine.
The device recognition task is formidable. For example, the device recognition software must be able to determine that two polygons that overlay each other on different metal layers in the integrated circuit are plates of a capacitor as opposed to two metal conductors or a via. The information needed to make such determinations is typically contained in a set of “rules” that are input to the device recognition software. The rules are dependent on the particular fabrication facility. The number of rules in a typical rule set is typically in the thousands. The time and cost needed to create a set of rules for each fabrication process is a substantial barrier to lowering the cost of fabrication of integrated circuits. Hence, it would be advantageous to provide a device recognition engine that does not rely on a large complex rule set that can be used in the LVS verification systems.
The device recognition engine also computes various electrical parameters of the devices that it detects. These values are stored as part of each device instance. The parameter calculations must be specified in the rule set. The task of extracting parameter values is one of the most difficult aspects of writing device recognition rules.
There are analogous verification problems in the design and fabrication of complex systems that are constructed from a number of integrated circuits that are connected together by wire bonds or connected on circuit boards having multiple layers of wiring. Prior to the actual fabrication of the devices, the designer must be able to verify that the layout of the system is consistent with the schematic representation of the system. Unfortunately, there is no equivalent LVS checking system for such devices based on physical connectivity.